1. Field of the Invention
The present invention relates to the automatic layout of one or more devices forming a circuit, especially an analog circuit, and, more particularly, to the automatic compaction of devices forming the circuit and the relocation of each device not forming part of the circuit to a position outside a boundary of the circuit.
2. Description of Related Art
Heretofore, the layout of devices forming an analog circuit, such as an operational amplifier or a comparator, included the manual or automated placement of a plurality of devices, e.g., transistors, in one conformal outline or in a group of adjacent conformal outlines. In some instances, this layout included the placement of all or part of one or more devices not associated with the circuit in one or more of the conformal outlines.
Once the initial layout of devices associated with the circuit (herein “member devices”) and devices not associated with the circuit (herein “nonmember devices”) was complete, it was often necessary for designers to manually manipulate the positions of one or more member devices and/or one or more nonmember devices in order to “compact” the circuit into a minimal space while adhering to design rules, such as a spacing constraint, for each member device and each nonmember device.
As used herein, the terms “compact”, “compaction” and the like, are utilized to refer to a process whereby one or more distances between member devices of a circuit and/or between the sides and/or the edges of one or more conformal outlines in which the member devices are received are adjusted, e.g., increased and/or decreased, as necessary, whereupon the resultant conformal outline(s) include(s) the member devices with no violations of any spacing constraints thereof in at least one of the horizontal and vertical directions. In addition, these terms also refer to the repositioning of all or part of one or more nonmember devices from inside the one or more conformal outlines to a position outside the one or more conformal outlines. The meaning of these terms, as used herein, is believed to be consistent with their usage by those of ordinary skill in the art to which the present invention pertains.
One problem with manual compaction is that optimal or near optimal compaction cannot be assured. Moreover, it is expensive and time consuming for a designer to perform manual compaction. Still further, there is no guarantee during manual compaction that the relative location of devices inside a conformal outline will be preserved. Lastly, there is no guarantee during manual compaction that the general shape of the conformal outline or a group of adjacent conformal outlines will be preserved.
It is, therefore, desirable to overcome the above problems and others by providing an automated circuit design layout compaction method that preserves relative locations of member devices inside a conformal outline; removes nonmember devices from inside these conformal outlines; ensures that the final circuit layout meets all of its design rules; compacts the conformal outlines and the member devices positioned therein while maintaining appropriate spacing between each member device; and preserves the general shape of the conformal outline during compaction. Still other desirable features will become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description.